Fin-type field-effect transistors (FinFETs) have three-dimensional, non-planar configurations including fin-like structures extending above substrates. The substrates may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon layers down to the oxide or other insulating layers thereof following photolithography. Active fin heights are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by oxide thickness and etched fin height. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein the source/drain regions are formed immediately following fin patterning. Gate-last procedures can involve making a dummy gate, fabricating other elements of the transistor, removing the dummy gate, and replacing the removed dummy gate with actual gate materials. FinFET devices including silicon germanium fins enable improvements in performance with respect to silicon-based devices. Channel materials including high germanium content offer potential for developing 7 nm and later nodes. The formation of silicon germanium or pure germanium on silicon is challenging due to the high lattice mismatch, which may be 3.6% or more. Growing such material can lead to high defect densities due to dislocations and stacking faults. The layers are accordingly grown very thick in order to trap most of the defects at the interface and relax the silicon germanium material as the growth progresses.